More on XINT1

Back to this after a week. Glad that I wrote down what I was up to so I can remember.

I am still trying to figure out where all the information is kept.

as far as I understand, the PIE stuff is described in the "system control and interrupts guide" and the rest of the interrupts stuff is described in "CPU and instruction set reference guide"

on p 6-18 of SCIG (system control and interrupts guide) XINT1 is INT1.4 and XINT2 is INT1.5. These are both MUXED into CPU INT1. I think that that means that XINT1 is higher priority than XINT2. The only higher priority interrupts are PDPINTA and PDPINTB (INT1.1 and INT1.2). I am unsure what they do.